• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An apparatus and method are provided for controlling TCLS in bit time units of a clock signal. The control signal generating circuit includes an input terminal, a first output terminal, and a second output terminal, and the control signal generating circuit receives an input signal input through the input terminal clocked to the clock signal, and the first signal is selected from the two states. In response to a test enable signal, output a column latch signal and a data input / output command signal having a first time interval to the first output terminal and the second output terminal, respectively, or the test enable having a second state among the two states. The column latch signal and the data input / output command signal having a second time interval are output to the first output terminal and the second output terminal in response to a signal, and the first time interval and the second time interval are the clock signal. Is controlled in bit time units, and the second time interval is controlled in bit time units of the clock signal to be shorter than the first time interval. Each of the first time interval and the second time interval is a time interval from when the column latch signal is activated until the data input / output command signal is activated.
    公开号:KR20040065661A
    申请号:KR1020030002756
    申请日:2003-01-15
    公开日:2004-07-23
    发明作者:최장석；임상규
    申请人:삼성전자주식회사；
    IPC主号:
    专利说明:

    Control signal generation circuit and control method for generating control signals controlled in bit time unit {Control signal generation circuit and control signal generation method for generating control signals controlled bit time}
    [8] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to an apparatus and a method for controlling TCLS in bit time units of a clock signal.
    [9] The semiconductor memory device selects one memory cell from a plurality of memory cells constituting the memory cell array through addressing, reads data stored in the selected memory cell through data read processing, or selects data through data write processing. Stored in memory cells.
    [10] 1 is a block diagram illustrating a conventional column selection and memory access operation. 2 is a timing diagram illustrating a conventional column selection and memory access operation.
    [11] A data read operation will be described with reference to FIGS. 1 and 2 as follows. Since row selection and memory access operations are well known in the art, description thereof will be omitted. The interface 10 receives a command signal CMD and an address Ai synchronized with the clock signal CLK through predetermined pins, not shown, and generates signals for controlling memory access. The control signals include a column latch signal COLLAT, a data input / output command signal COLCYC, and an address Ai '.
    [12] The interface 10 receives input data DIN and outputs a write data signal WD to the input / output sense amplifier 80, or receives and outputs a read data signal RD output to the input / output sense amplifier 80. The data signal Dout is output.
    [13] The column latch signal COLLAT is a control signal for latching the column address, and is a control signal indicating that the output address Ai 'is the selected column address. The data input / output command signal COLCYC is a control signal for controlling the operation of writing data to the selected column or the operation of reading data from the selected column, after the column latch signal COLLAT is activated as shown in FIG. 2. Is activated.
    [14] The functions of the column latch signal COLLAT and the data input / output command signal COLCYC and their relationships are well known in the art, and thus a detailed description thereof will be omitted.
    [15] The column address latch 30 outputs the column address CAi based on the received address Ai 'in response to the column latch signal COLLAT. The column decoder 20 receives the column latch signal COLLAT and the column address CAi and generates a column select line output signal CSL for driving the column select line corresponding to the column address CAi.
    [16] The column selector 50 outputs from the memory cell array 70 in response to the activated column select line output signal CSL, and detects and amplifies the bit line pairs BL and BLB that are sensed and amplified by the bit line sense amplifier 60. Transfer data to local I / O line pair (IO.IOB).
    [17] The input / output sense amplifier control circuit 40 generates an input / output sense amplifier enable signal PIOSE in response to the activated data input / output command signal COLCYC. The input / output sense amplifier 80 senses and amplifies the data of the local input / output line pair IO.IOB and reads the data of the local input / output line pair IO.IOB in response to the activated sense amplifier enable signal PIOSE. The data signal RD is transferred to the global input / output line pair GIO / GIOB.
    [18] That is, the column select line output signal CSL is activated in response to the activation of the column latch signal COLLAT, and is output from the memory cell array 70 in response to the activated column select line output signal CSL to sense the bit line. The data sensed and amplified by the amplifier 60 is transmitted to the local input / output line pairs IO and IOB, and the data of the local input / output line pairs IO and IOB are developed by the input / output sense amplifier 80 and developed. The data is transmitted to the global input / output line pair GIO / GIOB as read data RD in response to the data input / output command signal COLCYC that is activated after the column latch signal COLLAT is activated.
    [19] Referring to FIG. 2, TCLS represents a time from when the column latch signal COLLAT is activated until the data input / output command signal COLCYC is activated. Here, TCLS is 2tCK, tCK means one period of the clock signal CLK, and bit time means half of tCK. Thus, tCK is a 2-bit time.
    [20] Since a conventional semiconductor memory device cannot adjust the TCLS, when the operating frequency of the semiconductor memory device is higher than the operating frequency of the test device for testing the semiconductor memory device, the semiconductor memory device may be effectively used by the test device. You can't test it. Therefore, it is difficult to select a known good die (KGD) during the test.
    [21] Accordingly, the technical problem to be achieved by the present invention is to provide an apparatus and method capable of effectively performing a test by controlling TCLS in bit time units of a clock signal.
    [1] The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.
    [2] 1 is a block diagram illustrating a conventional column selection and memory access operation.
    [3] 2 is a timing diagram illustrating a conventional column selection and memory access operation.
    [4] 3 shows a control signal generating circuit according to the first embodiment of the present invention.
    [5] 4 is a timing diagram of a control signal generation circuit according to the first embodiment of the present invention.
    [6] 5 shows a control signal generating circuit according to the second embodiment of the present invention.
    [7] 6 shows a timing diagram of a control signal generation circuit according to the second embodiment of the present invention.
    [22] The control signal generating circuit according to the present invention includes an input terminal, a first output terminal, and a second output terminal, wherein the control signal generating circuit receives an input signal input through the input terminal clocked to a clock signal, and in two states. A column latch signal having a first time interval and a data input / output command signal are output to the first output terminal and the second output terminal in response to the test enable signal of the first state, or have a second state among the two states; In response to the test enable signal, output the column latch signal and the data input / output command signal having a second time interval to the first output terminal and the second output terminal, respectively, and the first time interval and the second time interval. Is controlled in bit time units of the clock signal, and the bit time stage of the clock signal is shorter than the first time interval. It is controlled to.
    [23] Each of the first time interval and the second time interval is a time interval from when the column latch signal is activated until the data input / output command signal is activated.
    [24] The control signal generating circuit according to the present invention comprises: a first latch clocked to a clock signal to latch an input signal; A second latch clocked to the clock signal to latch an output signal of the first latch; A selection circuit for outputting the output signal of the first latch or the output signal of the second latch as a column latch signal in response to a test enable signal; And a third latch clocked to the clock signal to latch the output signal of the second latch as a data input / output command signal, wherein a time until the data latch command is activated after the column latch signal is activated Is controlled in the bit time unit of the clock signal.
    [25] The control signal generating circuit according to the present invention comprises: a first latch clocked to a clock signal to latch an input signal; A second latch clocked to the clock signal to latch an output signal of the first latch; A third latch clocked to the clock signal to latch an output signal of the second latch; And
    [26] A selection circuit outputting an output signal of the second latch or an output signal of the third latch in response to a test enable signal; After the output signal of the first latch is activated, the time until the output signal of the selection circuit is activated is controlled in the bit time unit of the clock signal.
    [27] The control signal generating method according to the present invention comprises the steps of receiving a command signal inputted through the input terminal clock signal; And outputting a column latch signal and a data input / output command signal having a first time interval to the first output terminal and the second output terminal, respectively, in response to the test enable signal of the first state among the two states, or And outputting the column latch signal and the data input / output command signal having a second time interval to the first output terminal and the second output terminal, respectively, in response to the test enable signal having a second state. The one time interval and the second time interval are controlled in the bit time unit of the clock signal, and the second time interval is controlled in the bit time unit of the clock signal to be shorter than the first time interval.
    [28] The first time interval and the second time interval are time intervals after the column latch signal is activated until the data input / output command signal is activated.
    [29] In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.
    [30] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.
    [31] 3 shows a control signal generating circuit according to the first embodiment of the present invention. Referring to FIG. 3, the control signal generation circuit 300 is a circuit for generating a column latch signal COLLAT and a data input / output command signal COLCYC in a semiconductor device capable of writing / reading data to / from a memory cell array. , A circuit corresponding to the interface 10 shown in FIG. 1.
    [32] The control signal generation circuit 300 includes a first latch 310, a second latch 325, a third latch 345, and a selection circuit 335, and the first latch 310 has a clock signal CLK. Clock signal to latch the input signal IN, the second latch 325 is clocked to the clock signal CLK to latch the output signal of the first latch 310, and the selection circuit 335 is the test enable signal. The output signal INF1 of the first latch 310 or the output signal INF2 of the second latch 325 is output as the column latch signal COLLAT in response to the state of (TEST_EN) (for example, logic low or logic high). The third latch 345 is clocked to the clock signal CLK to latch the output signal INF2 of the second latch 325 as the data input / output command signal COLCYC, and the column latch signal COLLAT is activated. The time TCLS until the data input / output command signal COLCYC is activated is controlled in the bit time unit of the clock signal CLK.
    [33] The control signal generation circuit 300 shown in FIG. 3 is a circuit for adjusting the timing at which the column latch signal COLLAT is activated.
    [34] The control signal generation circuit 300 may include the first inverter 320, the second inverter 315, and the third considering the phase relationship between the input signal IN, the column latch signal COLLAT, and the data input / output command signal COLCYC. It further includes an inverter 330 and two buffers 340 and 350.
    [35] Accordingly, the control signal generation circuit 300 shown in FIG. 3 is just one embodiment proposed for convenience of explanation of the operation of the control signal generation circuit for controlling the TCLS according to the present invention in bit time units.
    [36] The first latch 310 receives the first signal 320 and the second inverter 315 through the output terminal QB in response to the falling edge of the clock signal CLK. To send. The input signal IN is a signal generated by decoding the data write command or the data read command. If the input signal IN is active high, the inverters 320, 315, and 330 are unnecessary.
    [37] The first inverter 320 is connected between the output terminal QB of the first latch 310 and the first input terminal A of the selection circuit 335 to invert the output signal INF1 of the first latch 310. The inverted output signal INF1B is output to the first input terminal A of the selection circuit 335.
    [38] The second inverter 315 is connected between the output terminal QB of the first latch 310 and the input terminal D of the second latch 325 to invert the output signal INF1 of the first latch 310. The inverted output signal INF1B is output to the input terminal D of the second latch 325.
    [39] The second latch 325 is clocked by the clock signal CLK to output the output signal INF1B of the second inverter 315 to the second input terminal B of the third inverter 330 and the selection circuit 335. . The third inverter 330 is connected between the output terminal Q of the second latch 325 and the input terminal D of the third latch 345.
    [40] The third latch 345 is clocked by the clock signal CLK to transmit the output signal INF2B of the third inverter 330 to the buffer 350. The buffer 350 buffers the output signal of the third latch 345 and outputs the result as the data input / output command signal COLCYC.
    [41] The selection circuit 335 outputs the output signal INF1B of the first inverter 320 or the output signal INF2 of the second latch 325 to the buffer 340 in response to the test enable signal TEST_EN. The buffer 340 buffers the output signal of the selection circuit 335 and outputs the result as the column latch signal COLLAT. The selection circuit 335 may be implemented as a 2-input-1 output multiplexer.
    [42] 4 is a timing diagram of a control signal generation circuit according to the first embodiment of the present invention. A method of adjusting TCLS will now be described with reference to FIGS. 3 and 4.
    [43] First, when the semiconductor device including the control signal generation circuit 300 operates normally (this is referred to as a normal mode), the selection circuit 335 has a test enable signal TEST_EN having a first state (for example, a logic low). In response to), a signal input to the first input terminal A, that is, a signal corresponding to the signal output from the first latch 310 is output as the column latch signal COLLAT.
    [44] Therefore, in the normal mode, the data input / output command signal COLCYC is activated after 2tCK after the column latch signal COLLAT is activated. That is, the data input / output command signal COLCYC is activated after 2tCK after the column latch signal COLLAT is activated by the second latch 325 and the third latch 350 that operate in synchronization with the clock signal CLK.
    [45] However, when a semiconductor device including the control signal generation circuit 300 is to be tested with a test device (this is called a test mode), the selection circuit 335 has a test enable having a second state (eg, logic high). In response to the signal TEST_EN, a signal input to the second input terminal B, that is, an output signal INF2 of the second latch 325 is output.
    [46] Therefore, in the test mode, the data input / output command signal COLCYC is activated after tCK after the column latch signal COLLAT is activated. That is, the data input / output command signal COLCYC is activated after tCK after the column latch signal COLLAT is activated by the third latch 350 operating in synchronization with the clock signal CLK.
    [47] The time at which the column latch signal COLLAT is activated in the test mode is 1 tCK (ie, 2 bit time) slower than the time at which the column latch signal COLLAT is activated in the normal mode.
    [48] Therefore, the control signal generation circuit 300 according to the present invention has the effect of reducing the TCLS from 2tCK to 1tCK. In addition, it is natural that the TCLS can be controlled by the bit time unit of the clock signal CLK by applying the idea according to the present invention.
    [49] 5 shows a control signal generating circuit according to the second embodiment of the present invention. The control signal generation circuit 500 illustrated in FIG. 5 is a circuit for adjusting the time point at which the data input / output command signal COLCYC is activated.
    [50] The control signal generation circuit 500 includes a first latch 510, a second latch 530, a third latch 540, and a selection circuit 545, and the first latch 510 includes a clock signal CLK. Clock signal to latch the input signal IN, the second latch 530 is clocked to the clock signal CLK to latch the output signal of the first latch 510, and the third latch 540 is the clock signal ( CLK) to latch the output signal of the second latch 530. The input signal IN is a signal generated by decoding the data write command signal CMD or the data read command signal CMD input to the interface 10 shown in FIG. 1.
    [51] The selection circuit 545 selectively outputs the output signal of the second latch 530 or the output signal of the third latch 540 in response to the state of the test enable signal TEST_EN (eg, logic low or logic high). TCLS is controlled by the bit time unit of the clock signal CLK.
    [52] The control signal generating circuit 500 may include the first inverter 520, the second inverter 515, and the third considering the phase relationship between the input signal IN, the column latch signal COLLAT, and the data input / output command signal COLCYC. It further includes an inverter 535 and two buffers 525 and 550. Therefore, the control signal generation circuit 500 shown in FIG. 5 is only one embodiment proposed for convenience of explanation of the operation of the control signal generation circuit according to the present invention.
    [53] The first latch 510 receives the first signal 520 and the second inverter 515 through the output terminal QB in response to the falling edge of the clock signal CLK. To send.
    [54] The first inverter 520 is connected between the output terminal QB of the first latch 510 and the input terminal of the buffer 525 to invert the output signal FC1 of the first latch 510 and invert the output signal ( FC1B) is output to the input terminal of the buffer 525. The buffer 525 buffers the output signal FC1B of the first inverter 520 and outputs the result as the column latch signal COLLAT.
    [55] The second inverter 515 is connected between the output terminal QB of the first latch 510 and the input terminal D of the second latch 530 to invert the output signal FC1 of the first latch 510. The inverted output signal FC1B is output to the input terminal D of the second latch 530.
    [56] The second latch 530 is clocked by the clock signal CLK to transmit the output signal FC1B of the first inverter 515 to the second input terminal B of the third inverter 535 and the selection circuit 545. . The third inverter 535 is connected between the output terminal Q of the second latch 530 and the input terminal D of the third latch 540.
    [57] The third latch 540 is clocked to the clock signal CLK to transmit the output signal of the third inverter 535 to the first input terminal A of the selection circuit 545.
    [58] The selection circuit 545 selects the output signal FC2 of the second latch 530 or the output signal of the third latch 540 in response to the state of the test enable signal TEST_EN (eg, logic low or logic high). To the buffer 550. The buffer 550 buffers the output signal of the selection circuit 545 and outputs the result as the data input / output command signal COLCYC. The selection circuit 545 may be implemented as a two input-1 output multiplexer.
    [59] 6 shows a timing diagram of a control signal generation circuit according to the second embodiment of the present invention. A method of adjusting TCLS will now be described with reference to FIGS. 5 and 6.
    [60] First, in the normal mode, the first latch 510 outputs a signal FC1 having a phase opposite to that of the input signal IN to the first inverter 520 in response to the falling edge of the clock signal CLK. The first inverter 520 inverts the output signal FC1 of the first latch 510 and outputs the inverted signal FC1B as the column latch signal COLLAT.
    [61] After 2tCK after the column latch signal COLLAT is activated, the selection circuit 545 selects a signal input to the first input terminal A in response to the test enable signal TEST_EN having a first state (for example, a logic low). To print.
    [62] Therefore, in the normal mode, the data input / output command signal COLCYC is activated after 2tCK after the column latch signal COLLAT is activated. That is, the data input / output command signal COLCYC is activated after 2tCK after the column latch signal COLLAT is activated by the second latch 530 and the third latch 540 which operate in synchronization with the clock signal CLK.
    [63] However, in the test mode, the selection circuit 545 is input to the second input terminal B in response to the test enable signal TEST_EN having the second state (eg, logic high), that is, of the second latch 530. Output the output signal.
    [64] Therefore, in the test mode, the data input / output command signal COLCYC is activated after tCK after the column latch signal COLLAT is activated.
    [65] The time at which the column latch signal COLLAT is activated in the test mode is 1tCK (ie, 2 bit time) earlier than the time at which the column latch signal COLLAT is activated in the normal mode.
    [66] Therefore, the control signal generation circuit 500 according to the present invention has the effect of reducing the TCLS from 2tCK to 1tCK. In addition, it is natural that the TCLS can be controlled by the bit time unit of the clock signal CLK by applying the idea according to the present invention.
    [67] Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
    [68] As described above, the control signal generation circuit and the control signal generation method according to the present invention can control the TCLS in the bit time unit of the clock signal, so that the operating frequency of the test apparatus for testing the semiconductor device having the control signal generation circuit is There is an effect that can overcome the limitations.
    权利要求:
    Claims (12)
    [1" claim-type="Currently amended] In the control signal generation circuit,
    Input terminal;
    A first output stage; And
    A second output stage,
    The control signal generation circuit,
    The input signal input through the input terminal is clocked to the clock signal and receives a column latch signal having a first time interval and a data input / output command signal in response to a test enable signal of a first state among two states. Respectively outputting the column latch signal and the data input / output command signal having a second time interval in response to the test enable signal having a second state among the two states; And output to the second output terminal, respectively,
    Wherein the first time interval and the second time interval are controlled in the bit time unit of the clock signal, and the second time interval is controlled in the bit time unit of the clock signal to be shorter than the first time interval. Control signal generation circuit.
    [2" claim-type="Currently amended] The control signal generating circuit of claim 1, wherein each of the first time interval and the second time interval is a time interval from when the column latch signal is activated until the data input / output command signal is activated.
    [3" claim-type="Currently amended] In the control signal generation circuit 300,
    A first latch clocked to the clock signal to latch the input signal;
    A second latch clocked to the clock signal to latch an output signal of the first latch;
    A selection circuit for outputting the output signal of the first latch or the output signal of the second latch as a column latch signal in response to a test enable signal; And
    A third latch clocked to the clock signal to latch an output signal of the second latch as a data input / output command signal,
    And after the column latch signal is activated, the time until the data input / output command signal is activated is controlled in bit time units of the clock signal.
    [4" claim-type="Currently amended] The method of claim 3, wherein the input signal is a signal generated by decoding a data write command signal or a data read command signal, and the input signal is activated in response to the corresponding data write command signal or the data read command signal. Control signal generation circuit, characterized in that.
    [5" claim-type="Currently amended] The method of claim 3, wherein the control signal generation circuit,
    A first inverter connected between an output terminal of the first latch and a first input terminal of the selection circuit;
    A second inverter connected between the output end of the first latch and the input end of the second latch; And
    And a third inverter connected between the output end of the second latch and the input end of the third latch,
    And an output terminal of the second latch is connected to a second input terminal of the selection circuit.
    [6" claim-type="Currently amended] The control signal generating circuit according to claim 3, wherein the output signal of the first latch is an inverted signal of the input signal.
    [7" claim-type="Currently amended] In the control signal generation circuit,
    A first latch clocked to the clock signal to latch the input signal;
    A second latch clocked to the clock signal to latch an output signal of the first latch;
    A third latch clocked to the clock signal to latch an output signal of the second latch; And
    A selection circuit outputting an output signal of the second latch or an output signal of the third latch in response to a test enable signal;
    And after the output signal of the first latch is activated, the time until the output signal of the selection circuit is activated is controlled in the bit time unit of the clock signal.
    [8" claim-type="Currently amended] The method of claim 7, wherein the control signal generation circuit,
    A first inverter for inverting the output of the first latch;
    A second inverter connected between the output end of the first latch and the input end of the second latch; And
    And a third inverter connected between the output end of the second latch and the input end of the third latch,
    And a first input terminal of the selection circuit is connected to an output terminal of the third latch, and a second input terminal is connected to an output terminal of the second latch.
    [9" claim-type="Currently amended] 8. The control signal generating circuit according to claim 7, wherein the output signal of the first latch is a column latch signal and the output signal of the selection circuit is a data input / output command signal.
    [10" claim-type="Currently amended] The control signal generating circuit according to claim 7, wherein the output signal of the first latch is an inverted signal of the input signal.
    [11" claim-type="Currently amended] In the control signal generation method,
    Receiving a command signal input through the input terminal by being clocked to the clock signal; and
    Among the two states, the column latch signal and the data input / output command signal having the first time interval are output to the first output terminal and the second output terminal in response to the test enable signal of the first state, or the second one of the two states. Outputting the column latch signal and the data input / output command signal having a second time interval to the first output terminal and the second output terminal in response to the test enable signal having two states,
    Wherein the first time interval and the second time interval are controlled in the bit time unit of the clock signal, and the second time interval is controlled in the bit time unit of the clock signal to be shorter than the first time interval. Control signal generation method.
    [12" claim-type="Currently amended] 12. The method of claim 11, wherein the first time interval and the second time interval are time intervals after the column latch signal is activated until the data input / output command signal is activated.
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    同族专利:
    公开号 | 公开日
    KR100546310B1|2006-01-26|
    US20040135616A1|2004-07-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2003-01-15|Application filed by 삼성전자주식회사
    2003-01-15|Priority to KR20030002756A
    2004-07-23|Publication of KR20040065661A
    2006-01-26|Application granted
    2006-01-26|Publication of KR100546310B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR20030002756A|KR100546310B1|2003-01-15|2003-01-15|Control signal generation circuit and control signal generation method for generating control signals controlled bit time|
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